描述:The LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.It is ideal for low power and low noise 3.3V applications. These 8 bit D-Type latchs are controlled by a latch enable input (LE) and an output enable input (OE). While the LE input is held at a high level, the Q outputswill follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consuption. All inputs and outputs are equipped with protection circuits against static discharge, giving
描述:ST 74LVQ373 OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING 数据手册,查找说明书,说明书,指南,手册,用户指南,使用说明,操作说明,说明书下载,说明书大全
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desc:The LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.It is ideal for low power and low noise 3.3V applications. These 8 bit D-Type latchs are controlled by a latch enable input (LE) and an output enable input (OE). While the LE input is held at a high level, the Q outputswill follow the data input precisely. When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consuption. All inputs and outputs are equipped with protection circuits against static discharge, giving